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--Note: while building Project do include sec_clk and seg7 files which i posted library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity c09 is port( rst,clk: in std_logic;       op0,op1,op2,op3: out std_logic_vector(6 downto 0)); end c09; architecture count of c09 is component sec_clk Port (            clk             : in  std_logic;            rst : in std_logic;            op  : out std_logic            );     end component;     component seg7 port(m: in integer range 0 to 15;      num: out std_logic_vector(6 downto 0)); end component; signal flag: std_logic; signa...

This code is generally used as component: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity seg7 is

library ieee; use ieee.std_logic_1164.all; entity seg7 is port(m: in std_logic_vector(3 downto 0);      num: out std_logic_vector(6 downto 0)); end seg7; architecture sseg of seg7 is begin process(m) begin if(m="0000") then num<="1000000"; elsif(m="0001") then num<="1111001"; elsif(m="0010") then num<="0100100"; elsif(m="0011") then num<="0110000"; elsif(m="0100") then num<="0011001"; elsif(m="0101") then num<="0010010"; elsif(m="0110") then num<="0000010"; elsif(m="0111") then num<="1111000"; elsif(m="1000") then num<="0000000"; elsif(m="1001") then num<="0010000"; else num<="1111111"; end if; end process; end sseg;

This is a clock divider code, just set the max-count value as per your requirenment. For ex. If I want 1Hz freq. set the max count to i/p freq value viz. 1sec = 1Hz Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below: 1sec  =  24000000  -- for i/p frequency of 24 MHz. To get your desired frequency just calculate the maxcount with the formula given below: max_count = 24000000 * (1/your required frequency) CODE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.numeric_std.all ; entity clk_div is Port ( Clk : in std_logic ; rst : in std_logic ; op : out std_logic ); end clk_div ; architecture behavioral of clk_div is constant max_count : natural := 24000000 ; -- I used 24MHz clock ...