Skip to main content

Testimonials

I'm a student from overseas university our most retarded professor ever, gave us absolutely no time for anything. We needed help with assignments and further with the final project. Then I came across Prasad's website and blog and saw he deals with DE2 board, however ours was DE2-70 board, so I took a shot in the dark and emailed Prasad to see if he can may be help us out. And sure enough he replied the next day and he was able to write VHDL code for DE2-70 board for close to 100 dollars. He gave us the code first, we tested the .sof file on the board and then we paid him the money. And all this took no more than 3 days!! Very nice person to deal with!! Anytime I need help with VHDL code, I know who to approach now! Thank you for your hardwork Prasadji, as I used to call you!! :) 

- Vikas Yadav

Popular posts from this blog

Website is being updated with new UI!

Hi E veryone , Pardon me. It took me very long to get back on managing this website. You all during some part of a time in your life, you get so busy that you forget what you actually need to do to keep up. I am moving whole code database on Github so you all will never face any problem with finding codes. Feel free to follow me on Github for updates. My Github: https://github.com/prasadp4009   Stay tuned for updates. Thank you all.

Blu ShopMart

A Bluetooth and RFID based Shopping trolly concept designed for today's world. If any company wants to have this product, contact me on: prasadp4009@gmail.com

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment. For ex. If I want 1Hz freq. set the max count to i/p freq value viz. 1sec = 1Hz Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below: 1sec  =  24000000  -- for i/p frequency of 24 MHz. To get your desired frequency just calculate the maxcount with the formula given below: max_count = 24000000 * (1/your required frequency) CODE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.numeric_std.all ; entity clk_div is Port ( Clk : in std_logic ; rst : in std_logic ; op : out std_logic ); end clk_div ; architecture behavioral of clk_div is constant max_count : natural := 24000000 ; -- I used 24MHz clock ...