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Showing posts from November, 2010

Display on VGA Monitor by FPGA(VHDL code Synthesizable, 640X480 resol, 60Hz)

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns.

The Video Synchronization file I created is VGAS which has 5 o/ps viz.
red_outgreen_outblue_outhoriz_sync_outvert_sync_outThese are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).