Skip to main content

About Me

My Resume: Prasad_Pandit_Resume.pdf 

Hello Everybody, I am Prasad Pandit an Electronics Engineer, a Freelancer. I completed my Engineering in 2012. I have a keen intrest in technology development and research. I am a beginner in VHDL, AVR and PCB designing. I am good at Single and Double layer PCB designing, Synthesizable VHDL coding, uC tinkering.

vhdlcodes.com is an initiative to help the Amatures and Beginners to get on development track. You can use this site to start with basic projects like blinking LED, Simple counter design etc. I have added some basic projects to start with you can check it in Project Archieves.

If you still want any basic projects like designing gates or if you want any tutorials on using Softwares like Quartus II, SOPC builder etc you can contact me. I will add it if I get sufficient response from your side.

VHDL is not that hard. Once you got it, You will be more valuable than Diamond. Never lose hope and don't ever try to give up. It takes time but yes it makes you even better.



"That man will win some other day, who loses with smile..."

Think VHDL in terms of Gates, Muxes, Flipflops, Clock, Register. Keep your C knowledge aside and you will find it easier than ever.
Enjoy Programming..

P.S. If you like our work, help us by paying through Paypal.

Mail me: prasadp4009@gmail.com
             prasadp4009@vhdlcodes.com

Youtube Channel: Pulsee250i






Popular posts from this blog

RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…