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Display on VGA Monitor by FPGA(VHDL code Synthesizable, 640X480 resol, 60Hz)

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns.

The Video Synchronization file I created is VGAS which has 5 o/ps viz.
  • red_out
  • green_out
  • blue_out
  • horiz_sync_out
  • vert_sync_out
These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).
For the pins check the your board manual.

The VGAS.vhd file can be used as common file for all your FPGA projects(for dividing 50Hz clock as I have used PLL which is already present on DE1 board. So if you have DE1 board its well and good you can directly use the code with the syncclk.vhd included. If dont just a minor modification in i/p clock signal with 25MHz in VGAS.vhd and removing syncclk.vhd and its component in VGAS.vhd will work.)

The Ballm.vhd is used to create display on Monitor. For DE1 users you can diretly program the SOF file i hav provided in download links.

Post your replies and comments. For the projects or querries you have you can mail me on prasadp4009@gmail.com .

Be the follower, if you like my posts.

Enjoy programming.

Video link: http://www.youtube.com/watch?v=QcCdkWG-rmM

Download links for files:


http://www.4shared.com/file/_7V3nyj9/Ballm.html
http://www.4shared.com/file/8pE2Yhz2/Ballm.html
http://www.4shared.com/file/mqnCQJs0/sycclk.html
http://www.4shared.com/file/JsUb67B4/VGAS.html

Comments

  1. Thanks a lot for this.

    ReplyDelete
  2. hye. do you have any tutorial on how to create font/letter on vga monitor using de1 board. I only know how to write in up1 board which use table.

    ReplyDelete

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(Input freq 24MHz., top-level entity DigiClock)

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…