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Interfacing (RAM) Onboard M4K memory blocks of Cyclone II Altera De1 board

This code shows how to store or interface the SRAM with any of your code. You can integrate this code in your projects for storing data. I will upload the interface of RAM with RTC code I designed for storing Date.

In this code I used the on-board M4K memory blocks on Altera DE1 board as RAM in 32 words i.e. 32 address locations of 4-bit. The RAM is initialized through Altera's MegaFunction IP Library. Comment if you don't know how to initialize RAM on any Altera board. I stored some variables like 2,4,6,8 on some starting locations to check if its working. I also added feature of manual address incrementation and data i/p.



For manual data entry you have to use four switches on Altera De1 board viz.
  • SW0 --LSB
  • SW1
  • SW2
  • SW3 --MSB
To write data press KEY3 and to increment address location press KEY0.

Read operation will be done Automatically, as I have interfaced the BCD to 7SEG (modified seg7.vhd in my previous posts) decoder directly to data out of RAM. You will get to see the stored digit on 7Seg display no.1.

You can directly interface the write enable, I/P and O/P of data and address in your code with only some minor changes.

If you have any qurries feel free to Comment directly on post instead of mailing me so other people will also get some help from it. You still can mail me your querries and Ideas at prasadp4009@gmail.com.

Download liks:
  • Main Entity sram_test.vhd     : sram_test.vhd
  • Altera DE1 Quartus .sof file  : sram.sof
  • Megafunction file                  : srm.vhd
  • Seg7 modified                      : seg7.vhd

Video:

Comments

  1. Can you add your top module that sets up the buttons and calls the entity?

    ReplyDelete

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VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

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max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…