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New Videos Check them Out..!!

Mail me if you have any querries: prasadp4009@gmail.com

The First Video is: Digital Alarm Clock



2) Calculator using 16x2 LCD and Keyboard:



3) PONG GAME:



4) Mario Bouncing on monitor;








Comments

  1. i want to interface spartan3s400pq208 with pc using ft245bm usb device. do you have any related vhdl codes?

    ReplyDelete
    Replies
    1. Hey buddy, ft245 is used for usb to fifo right? so you have to design a parallel protol for this. You can find it on opencores.org. feel lucky if you get. Else you have to design by your own.

      Delete
  2. Want to try some projects out. Can you post the codes to these projects? e.g. Calculator and Alarm Clock? Thanks.

    ReplyDelete
    Replies
    1. Hey Buddy, I have posted code for Alarm Clock. Check the home page for latest projects..

      Delete

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VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…

RTC on FPGA with manual set synthesizeble VHDL code.

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The text data is stored in a HEX file and is loaded onto the ROM of 32x8 byte size. It can be reconfigured easily.

I will be uploading code in short of time with some new features.

And after that be ready for a BMP decoder. Get ready with your pic to be seen on Monitor via FPGA.

Updated:

I didnt made  changes to code, if you program fpga 2 times without turning it off the code works(It worked on my DE1 board)
I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code.

Project zip Download: LCD_TEST.zip