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New Videos Check them Out..!!

Mail me if you have any querries: prasadp4009@gmail.com

The First Video is: Digital Alarm Clock



2) Calculator using 16x2 LCD and Keyboard:



3) PONG GAME:



4) Mario Bouncing on monitor;








Comments

  1. i want to interface spartan3s400pq208 with pc using ft245bm usb device. do you have any related vhdl codes?

    ReplyDelete
    Replies
    1. Hey buddy, ft245 is used for usb to fifo right? so you have to design a parallel protol for this. You can find it on opencores.org. feel lucky if you get. Else you have to design by your own.

      Delete
  2. Want to try some projects out. Can you post the codes to these projects? e.g. Calculator and Alarm Clock? Thanks.

    ReplyDelete
    Replies
    1. Hey Buddy, I have posted code for Alarm Clock. Check the home page for latest projects..

      Delete

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Popular posts from this blog

RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…