Skip to main content

PONG Game in VHDL

Hello Everybody. So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube.

I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof.
All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.)

So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to.

If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com

More projects on way.

Enjoy Programming..!!

The game files are as below.

Compiled file for DE1 users: Ballm.sof
Top level entity: PONG.vhd
Component files: sec_clk.vhd, seg7.vhd, manu_clk.vhd
VGAsync files: VGAS_DE2.vhd, VGAS.vhd

Project Zip: Pong.zip

Video: 


Comments

Post a Comment

Popular posts from this blog

RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…