Skip to main content

PONG Game in VHDL

Hello Everybody. So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube.

I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof.
All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.)

So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to.

If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com

More projects on way.

Enjoy Programming..!!

The game files are as below.

Compiled file for DE1 users: Ballm.sof
Top level entity: PONG.vhd
Component files: sec_clk.vhd, seg7.vhd, manu_clk.vhd
VGAsync files: VGAS_DE2.vhd, VGAS.vhd

Project Zip: Pong.zip

Video: 


Comments

Post a Comment

Popular posts from this blog

Website is being updated with new UI!

Hi E veryone , Pardon me. It took me very long to get back on managing this website. You all during some part of a time in your life, you get so busy that you forget what you actually need to do to keep up. I am moving whole code database on Github so you all will never face any problem with finding codes. Feel free to follow me on Github for updates. My Github: https://github.com/prasadp4009   Stay tuned for updates. Thank you all.

Blu ShopMart

A Bluetooth and RFID based Shopping trolly concept designed for today's world. If any company wants to have this product, contact me on: prasadp4009@gmail.com

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment. For ex. If I want 1Hz freq. set the max count to i/p freq value viz. 1sec = 1Hz Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below: 1sec  =  24000000  -- for i/p frequency of 24 MHz. To get your desired frequency just calculate the maxcount with the formula given below: max_count = 24000000 * (1/your required frequency) CODE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.numeric_std.all ; entity clk_div is Port ( Clk : in std_logic ; rst : in std_logic ; op : out std_logic ); end clk_div ; architecture behavioral of clk_div is constant max_count : natural := 24000000 ; -- I used 24MHz clock ...