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RTC Clock with Alarm in VHDL

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details.

The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code.

The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.)

Project Archieve: DigiClock.zip

Video:


Comments

  1. We are going to use DE2 board. so what kind of changers we have to do?

    ReplyDelete
  2. I downloaded the code above but its still not the code as in the video above. its the old code for RTC. Can u check that once please?

    ReplyDelete
  3. i am new to vhdl and the de0 board, i saw each files are seperate in your download file how to i make this into one file to be edited and work onto a de0 board for learning purposes?

    ReplyDelete
  4. i am new to the de0 board and altera, i see your code is separated, how to i compile each file into one to be modified to work on the de0 board? This is for only learning purposes. thank you for your kind cooperation in this matter.

    ReplyDelete
  5. The files in the zip file does not look like its the final version you used on your video, can you please update the zip folder. thank you very much.

    ReplyDelete

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RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…