Skip to main content

Knowing your AVR ATmega or ATtiny microcontroller

Posting after a long break.

Anyway, I suppose you are a bit familier with microcontrollers and what they do. So this post is all about choosing microcontroller for your project.

See, before selecting any microcontroller you should point out some things:

  1. The pin numbers and device interfaced:
  • Number of Inputs and Outputs required.
  • Types of Input and Output. (Analog, PWM, Digital)
       This is the first thing you should check that what kind of sensors you are using, LCDs, Buttons, Speakers etc. This gives you idea about the number of pins required.
       Ex. Say you are using POT as Analog input (1 ADC pin required) and connected it to a Speaker which has PWM as input(1 PWM pin required). For this you can choose ATtiny45 or 85 which has 8 pin interface with 6 pin usable. Theres no need to select ATmega controllers.

   2. The SPEED and POWER funda:
  • Speed required for your project. Like if it is using math library and you are using Multiplication in your code. You should select the higher speed controllers. For simple button interface any low speed grade controller will work.
  • Here theres a twist, ATmel provides wide variety in selection of controller. Say your application works on low voltage and you still want speed. 
  • For Ex. If you want a 16MHz at 5v and you buy ATmega8L (L stands for low voltage compaitability). Then you are going to face probelm as ATmega8 supports 16MHz at 5v. But ATmega8L supports only 12MHz at 5v and 8 MHz at 3.3v. And also ATmega8 dont work at 3.3v logic.
        Another example say you want 16MHz at 3.3v then theres another child in ATmega8 family i.e. ATmega8A (A for Advanced(may be :P)) which works at 16MHz and at 3.3v logic.

So before selecting and buying microcontrollers just go to ATmel site check all the datasheets for the childs of family and you will be able to select perfect one for your project.

One more thing to be noted is, when you buy a uC it comes with 1MHz internal clock pre-programmed. So, if you want to use 8MHz internal RC oscillator you have to set the fuses of uC. Similary for external crystal too.

    3. Another is SPACE:

       Here we concider 3 main Memories.
  • SRAM
  Flash memory for your program size. If its big try to optimize it first. If doesnt reduce further dont worry ATmel developed some fat babies like ATmega128 or ATmega256 for that.

EEPROM memory. If you are reusing too much data and storing it again you should keep check on the amount of data you are using and then the EEPROM to store it. (Use EEPROM only when you are storing Database values as the memory access time is higher.)

SRAM. If you dealing with big Strings or Floating point numbers choose the uC who have enough RAM to process your data readily.

SO thats all about Selection. We will start work Shortly. Till then Enjoy..!! :)


  1. Thank you for the valuable info.


Post a Comment

Popular posts from this blog

RTC on FPGA with manual set synthesizeble VHDL code.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…