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Additional info about Clock Divider

Hello Coders.
Its a long time I am posting. Busy in some things actually so didnt got time to update.

Anyway. I am posting this for our fellow coders who were encountering problem while simulating the code.

Problem: Getting slight diffrence in frequency (a bit lower) than desired.

Reason: The reason of this is the propogation delay of logic gates. As we are using adder and comparator in code for dividing frequency. This adds a slight delay at o/p. This can be easily observed in simulator.

Solution: Manipulate your input constant by some factor and simulate till you get desired result as we cant avoid propogation delay.

Hope you got it. If still not, mail me.

August will be a month of New Exciting projects. Includes all Hacking Arduino software. Android programming and VHDL. KEEP CHECKING.....

HAVE A GREAT TIME.

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VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)


CODE:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.numeric_std.all; entityclk_divisPort ( Clk :instd_logic; rst :instd_logic; op :outstd_logic ); endclk_div; architecturebehavioralofclk_divisconstant max_count :natural:=24000000; -- I used 24MHz clockbeginprocess(Clk,rst) variable count :naturalrange0to max_count; beginif rst ='0'…