Skip to main content

About Me

Image
By
My Resume: Prasad_Pandit_Resume.pdf 

Hello Everybody, I am Prasad Pandit an Electronics Engineer, a Freelancer. I completed my Engineering in 2012. I have a keen intrest in technology development and research. I am a beginner in VHDL, AVR and PCB designing. I am good at Single and Double layer PCB designing, Synthesizable VHDL coding, uC tinkering.

vhdlcodes.com is an initiative to help the Amatures and Beginners to get on development track. You can use this site to start with basic projects like blinking LED, Simple counter design etc. I have added some basic projects to start with you can check it in Project Archieves.

If you still want any basic projects like designing gates or if you want any tutorials on using Softwares like Quartus II, SOPC builder etc you can contact me. I will add it if I get sufficient response from your side.

VHDL is not that hard. Once you got it, You will be more valuable than Diamond. Never lose hope and don't ever try to give up. It takes time but yes it makes you even better.



"That man will win some other day, who loses with smile..."

Think VHDL in terms of Gates, Muxes, Flipflops, Clock, Register. Keep your C knowledge aside and you will find it easier than ever.
Enjoy Programming..

P.S. If you like our work, help us by paying through Paypal.

Mail me: prasadp4009@gmail.com
             prasadp4009@vhdlcodes.com

Youtube Channel: Pulsee250i



Popular posts from this blog

VHDL code for Clock Divider

By
This is a clock divider code, just set the max-count value as per your requirenment. For ex. If I want 1Hz freq. set the max count to i/p freq value viz. 1sec = 1Hz Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below: 1sec  =  24000000  -- for i/p frequency of 24 MHz. To get your desired frequency just calculate the maxcount with the formula given below: max_count = 24000000 * (1/your required frequency) CODE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.numeric_std.all ; entity clk_div is Port ( Clk : in std_logic ; rst : in std_logic ; op : out std_logic ); end clk_div ; architecture behavioral of clk_div is constant max_count : natural := 24000000 ; -- I used 24MHz clock ...
25 comments
Read More

RTC on FPGA with manual set synthesizeble VHDL code.

By
Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great. ( Input freq 24MHz ., top-level entity DigiClock )
14 comments
Read More

PONG Game in VHDL

By
Hello Everybody . So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube. I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof. All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.) So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to. If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com More projects on way. Enjoy Programming..!! The game files are as below. Compiled file for DE1 users: Ballm.sof Top level entity: PONG.vhd Component files: sec_clk.vhd , seg7.vhd , manu_clk....
4 comments
Read More