Technology Simplified

Hello Everybody . So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube. I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof. All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.) So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to. If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com More projects on way. Enjoy Programming..!! The game files are as below. Compiled file for DE1 users: Ballm.sof Top level entity: PONG.vhd Component files: sec_clk.vhd , seg7.vhd , manu_clk....

Hello Everybody. It seems you are having problem about how to initialize on-board memory using Megafunction Library and M4K blocks. (I am using Quartus II 10.1 SP1, but procees will be similar all other versions) So here are the steps of the solution: Start Quartus II and open new project.  

This code shows how to store or interface the SRAM with any of your code. You can integrate this code in your projects for storing data. I will upload the interface of RAM with RTC code I designed for storing Date. In this code I used the on-board M4K memory blocks on Altera DE1 board as RAM in 32 words i.e. 32 address locations of 4-bit. The RAM is initialized through Altera's MegaFunction IP Library . Comment if you don't know how to initialize RAM on any Altera board. I stored some variables like 2,4,6,8 on some starting locations to check if its working. I also added feature of manual address incrementation and data i/p.

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns. The Video Synchronization file I created is VGAS which has 5 o/ps viz. red_out green_out blue_out horiz_sync_out vert_sync_out These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes. VHDL code :

--Note: while building Project do include sec_clk and seg7 files which i posted library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity c09 is port( rst,clk: in std_logic;       op0,op1,op2,op3: out std_logic_vector(6 downto 0)); end c09; architecture count of c09 is component sec_clk Port (            clk             : in  std_logic;            rst : in std_logic;            op  : out std_logic            );     end component;     component seg7 port(m: in integer range 0 to 15;      num: out std_logic_vector(6 downto 0)); end component; signal flag: std_logic; signa...

This code is generally used as component: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity seg7 is