Technology Simplified

Hello Everybody, hope you must have liked the PONG and Alarm Clock codes. This is another video of PacMan game I designed, with storing the sprite images of fruit and PacMan in ROM and retrieving them accordingly. Heres video of it. Enjoy VHDL. More Codes ahead. Keep Following..!!

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details. The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code. The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.) Project Archieve: DigiClock.zip Video:

Hello Everybody . So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube. I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof. All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.) So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to. If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com More projects on way. Enjoy Programming..!! The game files are as below. Compiled file for DE1 users: Ballm.sof Top level entity: PONG.vhd Component files: sec_clk.vhd , seg7.vhd , manu_clk....

I have just found this code which is used by Columbia University Students in their projects. i would like to share it with you. It works probably with all Terasic Altera FPGA boards, Xilinx FPGA boards etc. The code is predesigned concidering 640x480 VGA resolution at 60Hz. But you can easily modify it using the VGA timing information from the site specified. Here are the links: For VGA timing    : http://martin.hinner.info/vga/timing.html VGA_Timing.vhd  : http://www.4shared.com/file/wdYoDlvR/vga_timing.html Don't forget to vote on polls. Mail me if you have any querries or want to do project at prasadp4009@vhdlcodes.com or prasadp4009@gmail.com . Enjoy Programming..!!

Its Done...!! The Frequency Counter or Measurer is ready. You can measure any I/P frequency from 3Hz to 95KHz i.e. (95,000 Hz for DE1 board Cyclone II FPGA).(This can be diffrent for difrent FPGAs according to their propogation delays and other time factors). Above this value the FPGA gets unstable and show at-random values. There are 3 levels of Accuracy Hz. (displayed value) x 10 Hz. (displayed value) x 100 Hz.  I have put a reset button, which is Pushbutton when clicked initiate the frequency measurement process. It then holds the value for user to read.

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great. ( Input freq 24MHz ., top-level entity DigiClock )

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns. The Video Synchronization file I created is VGAS which has 5 o/ps viz. red_out green_out blue_out horiz_sync_out vert_sync_out These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes. VHDL code :