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Hello Everybody, hope you must have liked the PONG and Alarm Clock codes. This is another video of PacMan game I designed, with storing the sprite images of fruit and PacMan in ROM and retrieving them accordingly. Heres video of it. Enjoy VHDL. More Codes ahead. Keep Following..!!

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details. The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code. The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.) Project Archieve: DigiClock.zip Video:

Hello Everybody . So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube. I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof. All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.) So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to. If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com More projects on way. Enjoy Programming..!! The game files are as below. Compiled file for DE1 users: Ballm.sof Top level entity: PONG.vhd Component files: sec_clk.vhd , seg7.vhd , manu_clk....

The code is designed using the 'VHDL function' to convert integer to bcd, more specifically binary to bcd. Features: Clock based as well as manual count Up and down count controlled using switch Push button to count manually LED to display count mode Asynchronous reset Post your comments, queries and suggestions   [Download links for project files are given below] Check Download Section or download from below. DE1 complete project: BCDUDOWNCOUNTER.zip Main entity: bcd_up_down_counter.vhd Components: manu_clk.vhd                     seg7.vhd

Hello Coders.  I am uploading a step by step tutorials for VHDL and working with Altera boards.. Which includes basic projects from this site.. Compiling them.. Using onboard components.. Do check them out on my youtube page. Here's the link for Tutorial Playlist: http://www.youtube.com/watch?v=x3sgK2HuCQg Suggest any modifications. I am going slow at some starting so everyone gets in phase easily. Mail your Queries @: prasadp4009@gmail.com

I have just found this code which is used by Columbia University Students in their projects. i would like to share it with you. It works probably with all Terasic Altera FPGA boards, Xilinx FPGA boards etc. The code is predesigned concidering 640x480 VGA resolution at 60Hz. But you can easily modify it using the VGA timing information from the site specified. Here are the links: For VGA timing    : http://martin.hinner.info/vga/timing.html VGA_Timing.vhd  : http://www.4shared.com/file/wdYoDlvR/vga_timing.html Don't forget to vote on polls. Mail me if you have any querries or want to do project at prasadp4009@vhdlcodes.com or prasadp4009@gmail.com . Enjoy Programming..!!