Technology Simplified

Hello Everybody. The LCD 16x2 code is ready. Just one bug which is still not recognized. You need to program code 2 times on board to see it work. I dont know why its behaving like that. The text data is stored in a HEX file and is loaded onto the ROM of 32x8 byte size. It can be reconfigured easily. I will be uploading code in short of time with some new features. And after that be ready for a BMP decoder. Get ready with your pic to be seen on Monitor via FPGA. Updated: I didnt made  changes to code, if you program fpga 2 times without turning it off the code works(It worked on my DE1 board) I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code. Project zip Download: LCD_TEST.zip

Hello Everybody, hope you must have liked the PONG and Alarm Clock codes. This is another video of PacMan game I designed, with storing the sprite images of fruit and PacMan in ROM and retrieving them accordingly. Heres video of it. Enjoy VHDL. More Codes ahead. Keep Following..!!

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details. The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code. The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.) Project Archieve: DigiClock.zip Video:

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns. The Video Synchronization file I created is VGAS which has 5 o/ps viz. red_out green_out blue_out horiz_sync_out vert_sync_out These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).