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Showing posts with the label vhdl fpga clock divider

RTC Clock with Alarm in VHDL

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details. The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code. The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.) Project Archieve: DigiClock.zip Video:

Additional info about Clock Divider

Hello Coders. Its a long time I am posting. Busy in some things actually so didnt got time to update. Anyway. I am posting this for our fellow coders who were encountering problem while simulating the code. Problem: Getting slight diffrence in frequency (a bit lower) than desired. Reason: The reason of this is the propogation delay of logic gates. As we are using adder and comparator in code for dividing frequency. This adds a slight delay at o/p. This can be easily observed in simulator. Solution: Manipulate your input constant by some factor and simulate till you get desired result as we cant avoid propogation delay. Hope you got it. If still not, mail me. August will be a month of New Exciting projects. Includes all Hacking Arduino software. Android programming and VHDL. KEEP CHECKING..... HAVE A GREAT TIME.