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Showing posts with the label memory blocks

Knowing your AVR ATmega or ATtiny microcontroller

Posting after a long break. Anyway, I suppose you are a bit familier with microcontrollers and what they do. So this post is all about choosing microcontroller for your project. See, before selecting any microcontroller you should point out some things: The pin numbers and device interfaced: Number of Inputs and Outputs required. Types of Input and Output. (Analog, PWM, Digital)        This is the first thing you should check that what kind of sensors you are using, LCDs, Buttons, Speakers etc. This gives you idea about the number of pins required.        Ex. Say you are using POT as Analog input (1 ADC pin required) and connected it to a Speaker which has PWM as input(1 PWM pin required). For this you can choose ATtiny45 or 85 which has 8 pin interface with 6 pin usable. Theres no need to select ATmega controllers.    2. The SPEED and POWER funda: Speed required for your project. Like if it is using math...

Initializing M4K blocks for RAM. (For Altera FPGA users)

Hello Everybody. It seems you are having problem about how to initialize on-board memory using Megafunction Library and M4K blocks. (I am using Quartus II 10.1 SP1, but procees will be similar all other versions) So here are the steps of the solution: Start Quartus II and open new project.  

Interfacing (RAM) Onboard M4K memory blocks of Cyclone II Altera De1 board

This code shows how to store or interface the SRAM with any of your code. You can integrate this code in your projects for storing data. I will upload the interface of RAM with RTC code I designed for storing Date. In this code I used the on-board M4K memory blocks on Altera DE1 board as RAM in 32 words i.e. 32 address locations of 4-bit. The RAM is initialized through Altera's MegaFunction IP Library . Comment if you don't know how to initialize RAM on any Altera board. I stored some variables like 2,4,6,8 on some starting locations to check if its working. I also added feature of manual address incrementation and data i/p.