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Showing posts with the label VHDL Codes. Tips

16x2 LCD Controller in VHDL

Hello Everybody. The LCD 16x2 code is ready. Just one bug which is still not recognized. You need to program code 2 times on board to see it work. I dont know why its behaving like that. The text data is stored in a HEX file and is loaded onto the ROM of 32x8 byte size. It can be reconfigured easily. I will be uploading code in short of time with some new features. And after that be ready for a BMP decoder. Get ready with your pic to be seen on Monitor via FPGA. Updated: I didnt made  changes to code, if you program fpga 2 times without turning it off the code works(It worked on my DE1 board) I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code. Project zip Download: LCD_TEST.zip

Another VHDL game... PacMan

Hello Everybody, hope you must have liked the PONG and Alarm Clock codes. This is another video of PacMan game I designed, with storing the sprite images of fruit and PacMan in ROM and retrieving them accordingly. Heres video of it. Enjoy VHDL. More Codes ahead. Keep Following..!!

RTC Clock with Alarm in VHDL

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details. The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code. The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.) Project Archieve: DigiClock.zip Video:

PONG Game in VHDL

Hello Everybody . So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube. I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof. All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.) So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to. If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com More projects on way. Enjoy Programming..!! The game files are as below. Compiled file for DE1 users: Ballm.sof Top level entity: PONG.vhd Component files: sec_clk.vhd , seg7.vhd , manu_clk....

Initializing M4K blocks for RAM. (For Altera FPGA users)

Hello Everybody. It seems you are having problem about how to initialize on-board memory using Megafunction Library and M4K blocks. (I am using Quartus II 10.1 SP1, but procees will be similar all other versions) So here are the steps of the solution: Start Quartus II and open new project.