Technology Simplified

Its Done...!! The Frequency Counter or Measurer is ready. You can measure any I/P frequency from 3Hz to 95KHz i.e. (95,000 Hz for DE1 board Cyclone II FPGA).(This can be diffrent for difrent FPGAs according to their propogation delays and other time factors). Above this value the FPGA gets unstable and show at-random values. There are 3 levels of Accuracy Hz. (displayed value) x 10 Hz. (displayed value) x 100 Hz.  I have put a reset button, which is Pushbutton when clicked initiate the frequency measurement process. It then holds the value for user to read.

--Note: while building Project do include sec_clk and seg7 files which i posted library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity c09 is port( rst,clk: in std_logic;       op0,op1,op2,op3: out std_logic_vector(6 downto 0)); end c09; architecture count of c09 is component sec_clk Port (            clk             : in  std_logic;            rst : in std_logic;            op  : out std_logic            );     end component;     component seg7 port(m: in integer range 0 to 15;      num: out std_logic_vector(6 downto 0)); end component; signal flag: std_logic; signa...

This code is generally used as component: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity seg7 is