0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component sec_clk
Port (
           clk             : in  std_logic;
           rst : in std_logic;
           op  : out std_logic
           );
    end component;
   
component seg7
port(m: in integer range 0 to 15;
     num: out std_logic_vector(6 downto 0));
end component;


signal flag: std_logic;
signal a: integer range 0 to 10;
signal b: integer range 0 to 10;
signal c: integer range 0 to 10;
signal d: integer range 0 to 10;
begin

c1: sec_clk port map(clk,rst,flag);

process(rst,flag)
variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 10:=0;
variable m2: integer range 0 to 10:=0;
variable m3: integer range 0 to 10:=0;

begin

if rst='0' then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= 9 then
m0:= m0 + 1;
elsif m0=9 and m1 /= 9 then
m0:=0;
m1:= m1 + 1;
elsif m1=9 and m2 /= 9 and m0=9 then
m1:=0;
m0:=0;
m2:= m2 + 1;
elsif m2=9 and m3/= 9 and m0=9 and m1=9 then
m1:=0;
m0:=0;
m2 :=0;
m3 := m3 + 1;
elsif m3=9 then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
end if;
end if;

end process;

z0: seg7 port map(a,op0);
z1: seg7 port map(b,op1);
z2: seg7 port map(c,op2);
z3: seg7 port map(d,op3);

end count;



 here is my youtube video of above project: http://www.youtube.com/watch?v=RrPzS5FLz3k