Technology Simplified

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details. The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code. The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.) Project Archieve: DigiClock.zip Video:

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great. ( Input freq 24MHz ., top-level entity DigiClock )

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes. VHDL code :

--Note: while building Project do include sec_clk and seg7 files which i posted library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity c09 is port( rst,clk: in std_logic;       op0,op1,op2,op3: out std_logic_vector(6 downto 0)); end c09; architecture count of c09 is component sec_clk Port (            clk             : in  std_logic;            rst : in std_logic;            op  : out std_logic            );     end component;     component seg7 port(m: in integer range 0 to 15;      num: out std_logic_vector(6 downto 0)); end component; signal flag: std_logic; signa...

This code is generally used as component: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity seg7 is