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Hello Everybody. The LCD 16x2 code is ready. Just one bug which is still not recognized. You need to program code 2 times on board to see it work. I dont know why its behaving like that. The text data is stored in a HEX file and is loaded onto the ROM of 32x8 byte size. It can be reconfigured easily. I will be uploading code in short of time with some new features. And after that be ready for a BMP decoder. Get ready with your pic to be seen on Monitor via FPGA. Updated: I didnt made  changes to code, if you program fpga 2 times without turning it off the code works(It worked on my DE1 board) I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code. Project zip Download: LCD_TEST.zip

Hello Everybody . So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube. I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof. All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.) So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to. If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com More projects on way. Enjoy Programming..!! The game files are as below. Compiled file for DE1 users: Ballm.sof Top level entity: PONG.vhd Component files: sec_clk.vhd , seg7.vhd , manu_clk....

The code is designed using the 'VHDL function' to convert integer to bcd, more specifically binary to bcd. Features: Clock based as well as manual count Up and down count controlled using switch Push button to count manually LED to display count mode Asynchronous reset Post your comments, queries and suggestions   [Download links for project files are given below] Check Download Section or download from below. DE1 complete project: BCDUDOWNCOUNTER.zip Main entity: bcd_up_down_counter.vhd Components: manu_clk.vhd                     seg7.vhd

I have just found this code which is used by Columbia University Students in their projects. i would like to share it with you. It works probably with all Terasic Altera FPGA boards, Xilinx FPGA boards etc. The code is predesigned concidering 640x480 VGA resolution at 60Hz. But you can easily modify it using the VGA timing information from the site specified. Here are the links: For VGA timing    : http://martin.hinner.info/vga/timing.html VGA_Timing.vhd  : http://www.4shared.com/file/wdYoDlvR/vga_timing.html Don't forget to vote on polls. Mail me if you have any querries or want to do project at prasadp4009@vhdlcodes.com or prasadp4009@gmail.com . Enjoy Programming..!!

Mail me if you have any querries: prasadp4009@gmail.com The First Video is: Digital Alarm Clock 2) Calculator using 16x2 LCD and Keyboard: 3) PONG GAME: 4) Mario Bouncing on monitor;

Its Done...!! The Frequency Counter or Measurer is ready. You can measure any I/P frequency from 3Hz to 95KHz i.e. (95,000 Hz for DE1 board Cyclone II FPGA).(This can be diffrent for difrent FPGAs according to their propogation delays and other time factors). Above this value the FPGA gets unstable and show at-random values. There are 3 levels of Accuracy Hz. (displayed value) x 10 Hz. (displayed value) x 100 Hz.  I have put a reset button, which is Pushbutton when clicked initiate the frequency measurement process. It then holds the value for user to read.

Hello Everybody. It seems you are having problem about how to initialize on-board memory using Megafunction Library and M4K blocks. (I am using Quartus II 10.1 SP1, but procees will be similar all other versions) So here are the steps of the solution: Start Quartus II and open new project.  

This code shows how to store or interface the SRAM with any of your code. You can integrate this code in your projects for storing data. I will upload the interface of RAM with RTC code I designed for storing Date. In this code I used the on-board M4K memory blocks on Altera DE1 board as RAM in 32 words i.e. 32 address locations of 4-bit. The RAM is initialized through Altera's MegaFunction IP Library . Comment if you don't know how to initialize RAM on any Altera board. I stored some variables like 2,4,6,8 on some starting locations to check if its working. I also added feature of manual address incrementation and data i/p.

--Note: while building Project do include sec_clk and seg7 files which i posted library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity c09 is port( rst,clk: in std_logic;       op0,op1,op2,op3: out std_logic_vector(6 downto 0)); end c09; architecture count of c09 is component sec_clk Port (            clk             : in  std_logic;            rst : in std_logic;            op  : out std_logic            );     end component;     component seg7 port(m: in integer range 0 to 15;      num: out std_logic_vector(6 downto 0)); end component; signal flag: std_logic; signa...

This code is generally used as component: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity seg7 is

This is a clock divider code, just set the max-count value as per your requirenment. For ex. If I want 1Hz freq. set the max count to i/p freq value viz. 1sec = 1Hz Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below: 1sec  =  24000000  -- for i/p frequency of 24 MHz. To get your desired frequency just calculate the maxcount with the formula given below: max_count = 24000000 * (1/your required frequency) CODE: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 library IEEE ; use IEEE.STD_LOGIC_1164.ALL ; use IEEE.numeric_std.all ; entity clk_div is Port ( Clk : in std_logic ; rst : in std_logic ; op : out std_logic ); end clk_div ; architecture behavioral of clk_div is constant max_count : natural := 24000000 ; -- I used 24MHz clock ...