VHDL code for Clock Divider

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec  =  24000000  -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)

CODE:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity clk_div is Port ( Clk : in std_logic; rst : in std_logic; op : out std_logic ); end clk_div; architecture behavioral of clk_div is constant max_count : natural := 24000000; -- I used 24MHz clock begin process(Clk,rst) variable count : natural range 0 to max_count; begin if rst = '0' then count := 0; op <= '1'; elsif rising_edge(Clk) then if count < (max_count/2)-1 then op <='1'; count := count + 1; elsif count < max_count-1 then op <='0'; count := count + 1; else count := 0; op <='1'; end if; end if; end process; end behavioral;