Additional info about Clock Divider
Its a long time I am posting. Busy in some things actually so didnt got time to update.
Anyway. I am posting this for our fellow coders who were encountering problem while simulating the code.
Problem: Getting slight diffrence in frequency (a bit lower) than desired.
Reason: The reason of this is the propogation delay of logic gates. As we are using adder and comparator in code for dividing frequency. This adds a slight delay at o/p. This can be easily observed in simulator.
Solution: Manipulate your input constant by some factor and simulate till you get desired result as we cant avoid propogation delay.
Hope you got it. If still not, mail me.
August will be a month of New Exciting projects. Includes all Hacking Arduino software. Android programming and VHDL. KEEP CHECKING.....
HAVE A GREAT TIME.